It is well known that the gain of an operational amplifier can be increased by adding gain stages in cascade formation. However, there are some circumstances in which this is not a practical solution; i.e., each additional gain stage increases the phase shifts and makes frequency compensation more difficult. An alternative to additional stages is to increase the gain available from existing stages. One configuration for increasing amplification in a single stage is a cascode configuration. Cascode stages increase the voltage gain of an amplifier by means of boosting its effective output impedance. FIG. 1 shows a telescopic cascode operational transconductance amplifier (OTA). Cascode amplifiers are described in Microelectronic Circuits, 3rd ed., Sedra & Smith, 1991, pp. 734-738, Design of Analog-Digital BLSI Circuits for Telecommunications and Signal Processing, 2nd ed., edited by Franka & Tsividis, 1994, pp. 27-39, and U.S. Pat. No. 4,714,895, to Nicollini et al. Some of the advantages of this type of amplifier are high bandwidth and low current requirements. As will be described below, one of the problems with this type of amplifier is that the common-mode voltage must be carefully regulated. The present invention addresses this problem.
The need to regulate the common-mode voltage of the telescopic cascode operational transconductance amplifier can be better understood by examining its method of operation. As shown in FIG. 1, the amplifier includes NMOS transistors M5, M6, M7, M8 and M13, and PMOS transistors M9, M10, M11, and M12. NMOS transistors M5 and M6 form an input differential pair which are in series with NMOS transistors M7 and M8, respectively, which are the cascode transistors. The load stage of the amplifier of FIG. 1 also has to be cascoded in order to increase its effective impedance to a level comparable with the input differential pair. Thus, the PMOS load transistors M11 and M12 are connected in series with PMOS transistors M9 and M10, respectively, which serve as the cascode load transistors. The positive input 86 and negative input 88 of the amplifier are provided at the gates of the NMOS transistors M5 and M6. The gates of NMOS transistors M7 and M8 are connected to one another and receive the bias input 97. The gates of PMOS transistors M11 and M12 are connected to one another and receive bias input 99, and the gates of PMOS transistors M9 and M10 are connected to one another and receive bias input 98. The sources of transistors M5 and M6 are connected to the drain of NMOS transistor M13, which receives the common-mode input 96 on its gate. Common-mode input 96 controls the common-mode voltage of the outputs 90 and 92 by adjusting the voltage drop across NMOS transistor M13, which shifts the relative common-mode voltage level of the amplifier.
As can be seen from the construction of the amplifier, one of the reasons why the common-mode input 96 must be carefully controlled is that either side of the amplifier has two PMOS transistors and three NMOS transistors between the power supply rails and the output 90 or 92. As described in more detail below, this number of transistors limits the maximum achievable output voltage swings of the amplifier because a certain minimum voltage drop must occur across each of the transistors, and the sum of these voltage drops determines how close the voltage swings can come to the power supply rail voltages. One of the normal techniques for compensating for the limited voltage swing in the amplifier is to bias the transistors at the very edges of their operating ranges so as to achieve the minimum voltage drop possible across the transistors. As described in U.S. Pat. No. 4,714,895, to Nicollini et al., this technique allows for the maximum output voltage swing possible. For example, with reference to FIG. 1, the bias inputs 97, 98 and 99 are preferably restricted by such limits as to allow the widest possible excursion of the output signal. By terming V.sub.GS the gate source voltage of the transistors of the circuit, and V.sub.DSAT the minimum saturation drain voltage (V.sub.DSAT =V.sub.GS -V.sub.T, V.sub.T being the threshold voltage), these limits dictate that: bias input 99 must be a V.sub.GS below V.sub.DD ; bias input 98 must be a V.sub.GS +V.sub.DSAT below V.sub.DD ; and bias input 97 must be a V.sub.GS +2V.sub.DSAT above V.sub.SS. Furthermore, the voltage reference for the input signal must be a V.sub.GS +V.sub.DSAT above V.sub.SS, while the common-mode input 96 for the common-mode feedback circuit must be a V.sub.GS above V.sub.SS. With these limits on the biasing voltages, the allowable excursion range of the output signal spans from V.sub.SS +3V.sub.DSAT on the negative to V.sub.DD -2V.sub.DSAT on the positive. Thus, the limited range over which the output voltage swings can occur requires that the common-mode voltage be carefully controlled in the range so that the desired amplification of the input signals can be achieved.
One prior art method for controlling a common-mode input is disclosed in U.S. Pat. No. 4,574,250 to Senderowicz, titled "Switched Capacitor Filter Utilizing a Differential Input and Output Circuit and Method." FIG. 2 in this application corresponds to FIG. 1 in that patent. Other somewhat similar prior art circuits are shown and described in Design of Analog-Digital BLSI Circuits for Telecommunications and Signal Processing, supra, pp. 30-31. In the Senderowicz patent, the circuit of FIG. 2 is described as having a switched capacitor input 22 with input terminals VI.sup.+ and VI.sup.-. The difference between the input voltages VI.sup.+ and VI.sup.- is the total input voltage VI, while the average of each of these inputs is zero. A balanced switch capacitor sampler 22 is shown diagrammatically in FIG. 2 as being comprised of two capacitors having an equal capacitance and switched at the input side by a switch 24 and at the output side by a switch 26. The output switch 26 is coupled to the input of an amplifier 28 which has balanced feedback loops 30 which include a pair of capacitors 32 of equal capacitance. The capacitance of capacitor 32 is ratioed to the capacitance of switched sampler 22. The output of operational amplifier 28 is comprised of a positive voltage output 34, VO.sup.+, and a negative voltage output 36, VO.sup.-. Outputs 34 and 36 are similarly coupled to a switch capacitor sampler 38 which serves as a common-mode feedback, again shown diagrammatically as two equal capacitances switched between the outputs 34 and 36, a center input 40, and grounded terminals 42 and a center terminal 44. The result of sampler 38 is to keep the average value of the two outputs 34 and 36 equal to zero without affecting the output voltage VO, which is equal to VO.sup.+ -VO.sup.-.
Thus, in FIG. 2, the common-mode input signal 40 is derived from an average of the two output signals VO.sup.+ and VO.sup.-. The technique of taking the common-mode input signal from a division of the two output signals across a set of capacitors is commonly used in switched capacitor or sample-and-hold amplifier circuits. A similar configuration is described in U.S. Pat. No. 4,714,895, to Nicollini et al., which has the two-capacitor feedback circuit implemented specifically with a telescopic cascode operational transconductance amplifier configuration and which uses two permanent feedback capacitors in addition to the two switchable ones. However, while these techniques do allow the common-mode input to be derived from the average of the two outputs, they do not allow the common-mode output voltage to be regulated at a specific level with the precision that is required for some applications.
The present invention is directed to providing an amplifier configuration for overcoming the foregoing and other disadvantages. More specifically, the present invention is directed to an amplifier which allows precise control of the common-mode output voltage at a specific level as is required for some applications.